1. Field of the Invention
The present invention relates to the formation of conductive lines on integrated circuits. It more specifically aims at forming low resistance conductive lines adapted, in particular, to forming inductance conductors for radiofrequency applications or lines for carrying a high current, for example, for microprocessor clock supply lines.
2. Discussion of the Related Art
Generally in the field of integrated circuit manufacturing, a succession of steps of metallization deposition meant to ensure the circuit interconnections is provided.
When a conductive line with a particularly low resistance is desired to be obtained, it can of course be provided to deposit a thicker metallization. However, this requires a specific manufacturing step and raises etching problems.
Another idea is to superpose two metallization layers to obtain a resulting metallization of double thickness.
An object of the present invention is to provide a novel method of manufacturing of conductive lines with a particularly low resistance which is compatible with conventional methods of formation of metallization levels on integrated circuits.
Generally, to achieve this and other objects, the present invention uses a conventional mode of deposition of two successive interconnection layers by previously etching a substrate so that the total metallization thickness is higher than the sum of the individual thicknesses of the two deposited layers.
More specifically, the present invention provides a method of formation of a conductive line on integrated circuits including the steps of etching a first insulator layer to create therein openings of predetermined width at the locations where the conductive line is to be formed; depositing and etching a first interconnection layer of a first thickness; and depositing and etching a second interconnection layer of a second thickness; the predetermined width being higher than twice the greatest of the two thicknesses, and lower than twice the sum of the thicknesses.
According to an embodiment of the present invention, the step of deposition and etching of the first interconnection layer is preceded by a step of formation of conductive spacers of a third thickness on the lateral walls of the openings, the predetermined width then being increased by twice the thickness of the spacers.
According to an embodiment of the present invention, the step of deposition and etching of the second interconnection layer is immediately preceded by the steps of depositing a second insulator layer; etching the second insulator layer to expose the first interconnection layer above the openings; and depositing a second etch stop layer.
According to an embodiment of the present invention, the first and second interconnection layers are layers of a conductor chosen from the group comprising aluminum, copper, and their alloys, possibly with silicon.
According to an embodiment of the present invention, the spacers are made of tungsten.
The present invention also provides a conductive line formed on a surface of a substrate, the upper surface of the substrate comprising an insulating layer in which is formed an opening of predetermined width at the location where the conductive line is to be formed, including a first interconnection layer of a first thickness and a second interconnection layer of a second thickness, the predetermined width being higher than twice the greatest of the two thicknesses, and lower than twice the sum of the thicknesses.
According to an embodiment of the present invention, several parallel openings are formed at a low distance from one another.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.